On Chip Variation (OCV) and Usage in STA Timing Analysis

On Chip Variation(OCV) is a concept for variation occurred in chip fabrication. And OCV will bring timing impact for chip/die in different location in wafer, and thus STA results will not match real timing in silicon.

What those variations contain?

OCV variation mainly contain variations during process:

1. Metal width slight variation from location to location, and thus metal resistance is impacted.
2. Metal spacing variation in different location for same wafer, thus capacitance will be impacted. 
3. Gate length/width variation from transistor to transistor, and cell delay will also be impacted.
4. And so on.

Besides process variation for location to location in same wafer, there also exists variation from semiconductor silicon wafer to wafer.
All those variations will impact our timing results, and may cause chip fail to work.

Those on chip variation are exists and can't be avoid, since we can't make each die/wafer exactly the same even we have try hard to do so.

How to solve OCV impact to timing?

We need to solve those timing issue, since the variations can be removed for our semiconductor process.
The solution is to add some timing margin to cover the timing impact due to those on chip variations.

We use timing derate/derating in STA to add margin for those variations.

Command in PrimeTime/PT is

integer set_timing_derate
   -early | -late
   [-rise] [-fall]
   [-data] [-clock] 
   [-cell_delay] [-net_delay] [-cell_check]
   [-static] [-dynamic]
   [-scalar] [-variation]
   [-aocvm_guardband] [-pocvm_guardband] [-pocvm_coefficient_scale_factor]
   [-increment]
   derate_value
   [object_list]

With following command:

set_timing_derate -late -data [expr 1+$X%]
set_timing_derate -late -clock [expr 1+$Y%]
set_timing_derate -early -clock  [expr 1-$Z%]

We can get following timing:

 

With those settings, we will add margin for setup timing check. And the margin number can be calculated by:

LaunchClockPathDelay * Y% + DataPathDelay * X% + CaptureClockPathDelay * Z%

This is the simplest OCV derate settings with a scale number for all cells, pathes, which may be too pessimistic.

We have also introduced AOCV/POCV in advanced nodes.
I will explain those concepts in following posts.

VCD File In Power Analysis

VCD Stands for Value Change Dump, VCD file is used for verilog simulation and power analysis.
VCD file is an ASCII format file include waveform information, this file is used by Verilog simulators.
VCD file fromat is defined by IEEE Standard 1364.

ICC procedure: dump layout window snapshot

proc dump_gif { filename } {
 gui_set_setting -window [gui_get_current_window -types Layout -mru] \
   -setting viewshot -value ${filename}.bmp
 exec convert ${filename}.bmp ${filename}.gif
 file delete ${filename}.bmp
}

ICC Useful Commands

Select routing between two pins:
change_selection [gui_get_routes_between_objects {phy/u_SE2DIFF/CKI phy/u_XE36MSC3/XC10}]

Write flat verilog netlist:

change_names -hierarchy -rules verilog
ungroup -all -flatten
write_verilog -no_core_filler_cells OUT/${mw_topLevel}_flat.v

Connect signal through hierarchies:

connect_pin -from fromPin -to listOfDestinationPins

ICC bug: Vias not visible in lower level:

Workaround:
Use the following cmd to change the view of a module to CEL view:
change_macro_view -reference phy_core -view CEL
Keep value "Default" in Settings -> View -> Child View Name

Set port properties:

set_attribute [get_port -all VDD] port_type Power
set_attribute [get_port -all VDD] direction Inout

Purge cells:

redirect /dev/null "remove_mw_cell -version_kept 0 place_opt_icc" --> SolvNet Article
Keeps last version of cell "place_opt_icc".

Get placement utilization of a certain area:

report_placement_utilization -coordinates {X1 Y1 X2 Y2}

Cell sizing:
Via menue: ECO -> size cell
or on the cmd line:

get_alternate_lib_cells phy_dig/clk_gating/icc_place792
size_cell phy_dig/clk_gating/icc_place792 TSMC_CLN90G_SC9NTHVT_SLOW_M40_0P9/BUFX3H1T10N

Report wire length:
report_net_statistics {net1 net2}

Skip route on nets:
set_net_routing_rule -rule default -reroute freeze [get_nets {list_of_nets}] --> SolvNet Article

Check logic vs. physical library:
check_library -logic lib/LM/phy_core_SLOW_125_0P9.db -mw_library_name phy_core -cells phy_core
Caution: FRAM view of the physical cell needs to exist, otherwise the check will fail!!!

Open the GUI of a certain command:
gui_show_form place_opt

Get default values of a command:
get_command_option_values -default -command clock_opt

Report layout statistics:
report_design -physical

eco-by-netlist-change command:
update_mw_design_eco -change_verilog OUT/verilog_netlist.v phy_core -top_module phy_core

Run eco route:
route_eco -auto -search_repair_loop 5 -utilize_dangling_wires -reroute modified_nets_first_then_others

Add padding to cells:
set_keepout_margin -outer {5 5 5 5} -macro_masters AVT20 -type hard --> SolvNet Article

Snapshot of graphical window:
gui_set_setting -window [gui_get_current_window -types Layout -mru] -setting viewshot -value xxx.png

List all loaded procedures:
info proc

Write verilog file:
write_verilog -no_pg_nets verilog_file.v

Write verilog file with power pins and power signals:
write_verilog -pg_ports -output_net_name_for_pg verilog_file.v

Using a file as input for a command:
route_group -nets [read [open nets_file.txt r]]

DeCap Cell (Decoupling Capacitors)

What are Decaps?

• Decaps are on-chip decoupling capacitors that are attached to the power mesh to decrease noise effects
• Decaps are most effective when placed closest to the loads

Why need Decap cells：

• Modern designs are very sensitive to noise due to the presence of a larger number of potential noise generators that eat into the noise margins built into a design. The power grid, which provides the Vdd and ground signals throughout the chips, is one of the most important sources of noise, since supply voltage variations can lead not only to problems related to spurious transitions in some cases, particularly when dynamic logic is used, but also to delay variations
• Signal integrity is emerging as a limiting factor in the nano regime VLSI chip designs as technology scales. This is especially true on global networks like power/ground networks where noise margins have been reduced greatly in VLSI designs due to decreasing supply voltages. For dynamic voltage fluctuations on a P/G network, adding decap is regarded as the most efficient way to reduce such noises.

Instantaneous Voltage Drop (IVD) is a part of the landscape in Deep Sub-Micron (DSM) design. IVD is a droop in rail voltage prompted by large amounts of simultaneous switching in a circuit. Problems with IVD are especially common to high speed memories, which have potentially thousands of cells switching at a time.

A design with enough rail-to-rail capacitance becomes resistant to the effects of IVD, as the capacitance acts as a charge reserve supplying local current sinks briefly for the time of the event.

As such, it has become common in the past decade to add dcaps to the areas of an IC that otherwise have no cells, or add dcaps directly to problem areas such as high speed memories.

However, DCAPs normally come with a quite serious down-side. They are leaky devices. Too many DCAPs in a design can push leakage beyond the thermal runaway point, or at least beyond the customer's expectations.

For these reasons, DCAP insertion is a subject that requires more than casual attention of the layout designer.

Tap Cell

1. What is a 'tap cell'

The basic idea with a global substrate tap methodology is to omit internal substrate taps from the standard cells and instead to sprinkle dedicated tap cells throughout the P&R layout. The process design rules require that no piece of source/drain diffusion (inside a standard cell) be more than some maximum distance away from the tap diffusion inside at least one of the sprinkled tap cells.

If we assume (for the time being at least) that we don't have visibility into the cells showing us the exact locations of source/drain diffusion regions and/or tap diffusion regions, the tap to diffusion spacing constraints outlined above translate into a maximum allowed distance between any part of a standard cell and the edge of a dedicated tap cell.

2. What is a 'tap layer'

A tap layer is just an extra drawing layer defined in your technology file. It is not used in a fab process and will not be streamed out.

3. Why I would want a 'tap cell'

You would want a tap cell to satisfy the design rules of your technology.

Gate-Array-Backfill (GBF) Cells

Nearly every chip being produced today faces at least one respin in the life of the project. Multiple respins are not uncommon. The financial pain of these engineering potholes can be alleviated by changing as few layers in the design as possible--two layers changed in a 10 layer design is a great savings over an all-layer respin.

However, the problem preventing metal-only spins is the common need for logic changes that require inserting and configuring new gates to change or fix the operation of the original design.

Up till the innovation of GBF cells, a designer had only one choice for anticipating a problem in the design and preventing a metal-only respin-spare gates. The concept of spare gates involves pre-placing inactive (with inputs tied off) gates in the empty areas of a design (or even in the crowded areas) before tapeout. These gates then can later be re-wired to provide new functions on a design which exhibits post-production problems.

There are two major downsides to using spare cells, however: first, they are connected to VSS and VDD and despite having their inputs tied off, they are still drawing static current; second, the designer may not have the right cell in the right place at the time of the ECO. The cells chosen in the beginning and their placement limit the possibilities when ECO time comes.

Gate Array Backfill (GBF) cells a solution to these limitations. These cells are simply collections of unwired transistors that can fill a design, taking no power until such time as metal is added on top of them, and wiring is configured to create nearly any combination of logical element.

The use of these cells is simple and elegant--ACELLS are placed in the design in empty areas prior to tapeout. Each ACELL is simply a collection of transistors--they come in many sizes. At the respin, the ACELLS in the layout are replaced with Backfill (BF) personality cells. No change is made to the diffusion layer just M1 and a contact layer. The cell is then transformed into, say, an OR gate, or a Flip-Flop.