- Decaps are on-chip decoupling capacitors that are attached to the power mesh to decrease noise effects
- Decaps are most effective when placed closest to the loads
Why need Decap cells:
- Modern designs are very sensitive to noise due to the presence of a larger number of potential noise generators that eat into the noise margins built into a design. The power grid, which provides the Vdd and ground signals throughout the chips, is one of the most important sources of noise, since supply voltage variations can lead not only to problems related to spurious transitions in some cases, particularly when dynamic logic is used, but also to delay variations
- Signal integrity is emerging as a limiting factor in the nano regime VLSI chip designs as technology scales. This is especially true on global networks like power/ground networks where noise margins have been reduced greatly in VLSI designs due to decreasing supply voltages. For dynamic voltage fluctuations on a P/G network, adding decap is regarded as the most efficient way to reduce such noises.
Instantaneous Voltage Drop (IVD) is a part of the landscape in Deep Sub-Micron (DSM) design. IVD is a droop in rail voltage prompted by large amounts of simultaneous switching in a circuit. Problems with IVD are especially common to high speed memories, which have potentially thousands of cells switching at a time.A design with enough rail-to-rail capacitance becomes resistant to the effects of IVD, as the capacitance acts as a charge reserve supplying local current sinks briefly for the time of the event.As such, it has become common in the past decade to add dcaps to the areas of an IC that otherwise have no cells, or add dcaps directly to problem areas such as high speed memories.However, DCAPs normally come with a quite serious down-side. They are leaky devices. Too many DCAPs in a design can push leakage beyond the thermal runaway point, or at least beyond the customer's expectations.For these reasons, DCAP insertion is a subject that requires more than casual attention of the layout designer.
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