Tuesday, February 24, 2009

Net delay in ICC timing report

Net delay in ICC timing report is displayed in the input pin connected to the net.

U3249/y (buf_d10w) 20.3900 42.7837 86.3139 r
n3002 (net) 1 11.0479 0.0000 86.3139 r
U3250/a (buf_d2m_hvt) 20.3900 0.4279 * 86.7417 r


We can see the net delay using report_delay_calculation is not 0.

icc_shell> report_delay_calculation -from U3249/y -to U3250/a

****************************************
Report : delay_calculation
Design : ***
Version: B-2008.09-ICC-SP5
Date : Tue Feb 24 22:40:46 2009
****************************************

From pin: U3249/y
To pin: U3250/a
Main Library Units: 0.001ns 0.001pF 1kOhm


Operating Conditions: ww_v099_t125_maxc Library: sc_lib

arc type: net
Annotated_delay rise: 0.427862
Annotated_delay fall: 0.427862
total delay rise, fall: 0.427862 , 0.427862


ICC report_timing log

****************************************
Report : timing
-path full
-delay max
-input_pins
-nets
-max_paths 1
-transition_time
-capacitance
Design : rsa
Version: B-2008.09-ICC-SP5
Date : Tue Feb 24 22:16:39 2009
****************************************

* Some/all delay information is back-annotated.

# A fanout number of 1000 was used for high fanout net computations.

Operating Conditions: ww_v099_t125_maxc Library: sc_lib

Startpoint: efi_rsa_send_data[46]
(input port)
Endpoint: sa_efi0/efi_rsa_send_data_q_reg[46]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Point Fanout Cap Trans Incr Path
----------------------------------------------------------------------------------------------
clock (input port clock) (rise edge) 0.0000 0.0000
input external delay 0.0000 0.0000 r
efi_rsa_send_data[46] (in) 15.3220 8.9702 8.9702 r
efi_rsa_send_data[46] (net) 1 4.4576 0.0000 8.9702 r
U3248/a (buf_d10w) 15.3220 0.0632 * 9.0334 r
U3248/y (buf_d10w) 10.3372 34.4874 43.5208 r
n3001 (net) 1 2.4215 0.0000 43.5208 r
U3249/a (buf_d10w) 10.3372 0.0094 * 43.5301 r
U3249/y (buf_d10w) 20.3900 42.7837 86.3139 r
n3002 (net) 1 11.0479 0.0000 86.3139 r
U3250/a (buf_d2m_hvt) 20.3900 0.4279 * 86.7417 r
U3250/y (buf_d2m_hvt) 133.8156 144.4690 231.2107 r
n3003 (net) 1 13.8762 0.0000 231.2107 r
U3251/a (buf_d2m_hvt) 133.8156 0.7055 * 231.9162 r
U3251/y (buf_d2m_hvt) 399.9278 407.3107 639.2269 r
n3004 (net) 1 43.3720 0.0000 639.2269 r
sa_efi0/C279/u442/a1 (nand2b_d2dm_hvt) 399.9278 6.1595 * 645.3865 r
sa_efi0/C279/u442/y (nand2b_d2dm_hvt) 269.8072 417.0488 1062.4353 f
sa_efi0/C279/n25 (net) 1 36.9462 0.0000 1062.4353 f
sa_efi0/C279/u609/a (inv_d30m_hvt) 269.8072 4.6215 * 1067.0568 f
sa_efi0/C279/u609/y (inv_d30m_hvt) 61.7449 84.7218 1151.7786 r
sa_efi0/N27 (net) 1 11.9103 0.0000 1151.7786 r
sa_efi0/efi_rsa_send_data_q_reg[46]/d (mdff_d10dm) 61.7449 0.3622 * 1152.1407 r
data arrival time 1152.1407

clock clk (rise edge) 833.0000 833.0000
clock network delay (ideal) 0.0000 833.0000
clock uncertainty -100.0000 733.0000
sa_efi0/efi_rsa_send_data_q_reg[46]/clk (mdff_d10dm) 0.0000 733.0000 r
library setup time -87.8789 645.1211
data required time 645.1211
----------------------------------------------------------------------------------------------
data required time 645.1211
data arrival time -1152.1407
----------------------------------------------------------------------------------------------
slack (VIOLATED) -507.0197


1

Friday, February 6, 2009

Physical Design Rule

What's Physical Design Rule

1. Interface between the circuit designer and process engineer
2. Guidelines for constructing process masks
3. Unit dimension: minimum line width
scalable design rules: lambda parameter
absolute dimensions: micron rules
4. Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur
5. A complete set includes
set of layers
intra-layer: relations between objects in the same layer
inter-layer: relations between objects on different layers


Why Physical Design Rule:
To be able to tolerate some level of fabrication errors such as
1. Mask misalignment
2. Dust
3. Process parameters (e.g., lateral diffusion)
4. Rough surfaces

Basic Physical Design Rule:
  1. Width (INTERNAL)
  2. Spacing (EXTERNAL)
  3. Overlap (ENCLOSE)
  4. Extension (ENCLOSE)
  5. Clearance (EXTERNAL, ENCLOSE)

For Logic Design Rule, please refer to http://vlsi-concept.blogspot.com/2009/01/design-rule-checking-drc.html

Thursday, February 5, 2009

ASIC Design Implementation Flow In Brief

  1. design setup;
  2. floorplan;
  3. placement;
  4. Clock Tree synthesis (CTS);
  5. routing;
  6. chip finishing( insert diode, insert filler, insert metal filler, add redundant via …);
  7. signoff flow ( StarRCXT, PT, DRC, LVS).


ASIC Design Flow In Brief

  1. chip specification;
  2. front end modeling, use C, C++ or System C/system verilog to do the modeling and simulation;
  3. design implementation in front end, verilgo or VHDL ;
  4. simulation;
  5. FPGA verification(optional);
  6. Synthesis, Design compiler , RTL to gate level netlist;
  7. Physical implementation.
  8. Post simulation ( simulation with back-annotate SDF)
  9. signoff ( StarRCXT, PrimeTime, Hercules).
  10. set data to foundry ( GDSII file ), OPC.
  11. manufacturing.
  12. Test and packaging.

Wednesday, February 4, 2009

Mapping File: Database Layer <==> Process Layer

Maps File:
    Map database layers to process layers conducting_layers, via_layers, marker_layers, remove_layers.

Layer Information:
    Resistance information is optional: RPSQ (for conductors) or RPV (for vias) overrides process file, if specified
    via_layers: need to be mapped to the corresponding physical layers
    removed_layers: Those layers do not need to do extraction

Map file Example:
    http://gudonghua.googlepages.com/map-file-example.map.txt