Gate-Array-Backfill (GBF) Cells

Nearly every chip being produced today faces at least one respin in the life of the project. Multiple respins are not uncommon. The financial pain of these engineering potholes can be alleviated by changing as few layers in the design as possible--two layers changed in a 10 layer design is a great savings over an all-layer respin.

However, the problem preventing metal-only spins is the common need for logic changes that require inserting and configuring new gates to change or fix the operation of the original design.

Up till the innovation of GBF cells, a designer had only one choice for anticipating a problem in the design and preventing a metal-only respin-spare gates. The concept of spare gates involves pre-placing inactive (with inputs tied off) gates in the empty areas of a design (or even in the crowded areas) before tapeout. These gates then can later be re-wired to provide new functions on a design which exhibits post-production problems.

There are two major downsides to using spare cells, however: first, they are connected to VSS and VDD and despite having their inputs tied off, they are still drawing static current; second, the designer may not have the right cell in the right place at the time of the ECO. The cells chosen in the beginning and their placement limit the possibilities when ECO time comes.

Gate Array Backfill (GBF) cells a solution to these limitations. These cells are simply collections of unwired transistors that can fill a design, taking no power until such time as metal is added on top of them, and wiring is configured to create nearly any combination of logical element.

The use of these cells is simple and elegant--ACELLS are placed in the design in empty areas prior to tapeout. Each ACELL is simply a collection of transistors--they come in many sizes. At the respin, the ACELLS in the layout are replaced with Backfill (BF) personality cells. No change is made to the diffusion layer just M1 and a contact layer. The cell is then transformed into, say, an OR gate, or a Flip-Flop.