ICC Useful Commands

Select routing between two pins:
change_selection [gui_get_routes_between_objects {phy/u_SE2DIFF/CKI phy/u_XE36MSC3/XC10}]

Write flat verilog netlist:

change_names -hierarchy -rules verilog
ungroup -all -flatten
write_verilog -no_core_filler_cells OUT/${mw_topLevel}_flat.v

Connect signal through hierarchies:

connect_pin -from fromPin -to listOfDestinationPins

ICC bug: Vias not visible in lower level:

Workaround:
Use the following cmd to change the view of a module to CEL view:
change_macro_view -reference phy_core -view CEL
Keep value "Default" in Settings -> View -> Child View Name

Set port properties:

set_attribute [get_port -all VDD] port_type Power
set_attribute [get_port -all VDD] direction Inout

Purge cells:

redirect /dev/null "remove_mw_cell -version_kept 0 place_opt_icc" --> SolvNet Article
Keeps last version of cell "place_opt_icc".

Get placement utilization of a certain area:

report_placement_utilization -coordinates {X1 Y1 X2 Y2}

Cell sizing:
Via menue: ECO -> size cell
or on the cmd line:

get_alternate_lib_cells phy_dig/clk_gating/icc_place792
size_cell phy_dig/clk_gating/icc_place792 TSMC_CLN90G_SC9NTHVT_SLOW_M40_0P9/BUFX3H1T10N

Report wire length:
report_net_statistics {net1 net2}

Skip route on nets:
set_net_routing_rule -rule default -reroute freeze [get_nets {list_of_nets}] --> SolvNet Article

Check logic vs. physical library:
check_library -logic lib/LM/phy_core_SLOW_125_0P9.db -mw_library_name phy_core -cells phy_core
Caution: FRAM view of the physical cell needs to exist, otherwise the check will fail!!!

Open the GUI of a certain command:
gui_show_form place_opt

Get default values of a command:
get_command_option_values -default -command clock_opt

Report layout statistics:
report_design -physical

eco-by-netlist-change command:
update_mw_design_eco -change_verilog OUT/verilog_netlist.v phy_core -top_module phy_core

Run eco route:
route_eco -auto -search_repair_loop 5 -utilize_dangling_wires -reroute modified_nets_first_then_others

Add padding to cells:
set_keepout_margin -outer {5 5 5 5} -macro_masters AVT20 -type hard --> SolvNet Article

Snapshot of graphical window:
gui_set_setting -window [gui_get_current_window -types Layout -mru] -setting viewshot -value xxx.png

List all loaded procedures:
info proc

Write verilog file:
write_verilog -no_pg_nets verilog_file.v

Write verilog file with power pins and power signals:
write_verilog -pg_ports -output_net_name_for_pg verilog_file.v

Using a file as input for a command:
route_group -nets [read [open nets_file.txt r]]