概览
==, !=, >, <, >=, <=, =~, !~
解释
== 等于
!= 不等于
> 大于
< 小于
>= 大于等于
<= 小于等于
=~ 匹配
!~ 不匹配
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ASCI/VLSI Basic Concept blog try to collect basic concept for ASIC IC Designs, including front-end and back-end.
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2008
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December
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- How to read ITF file to find the process technology
- What does '45-nm' mean
- Cell Degradation Design Rule
- Timing Arc
- cell degradation
- virtual clock
- difference between real clock and ideal clock
- Ideal Network Feature
- Clock Latency
- Definition of Timing Path
- Ideal Clock Feature
- filter_collection 可以使用的操作符
- difference between dc_shell and dc_shell-t
- WLM- Wire load Model
- Design Compiler Topographical Technology
- Synopsys Implementation Tool Guide
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December
(16)
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