- No DRC (capacitance, fanout, and transition) check for ideal net.
- Zero pin capacitance and net capacitance for timing calculation.
For ideal clock feature, please refer to:
http://vlsi-concept.blogspot.com/2008/12/ideal-clock-feature.html
ASCI/VLSI Basic Concept blog try to collect basic concept for ASIC IC Designs, including front-end and back-end.
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