Timing Arc

Timing Arc Definition:

Timing arcs, along with netlist interconnect information, are the paths followed by the path tracer during path analysis.

Each timing arc has a startpoint and an endpoint.

• The startpoint can be an input, output, or I/O pin.
• The endpoint is always an output pin or an I/O pin.
• The only exception is a constraint timing arc, such as a setup or hold constraint between two input pins.

There are two timing arc types:

1. combinational timing arc: combinational timing arc information is used to calculate the physical delays in timing propagation and to trace paths. The timing analyzer uses path-tracing arcs for circuit timing analysis.
2. sequential timing arc: sequential timing arc information is used to determine rule-based design optimization constraints.