Monday, December 29, 2008

How to read ITF file to find the process technology

The MinWidth of POLY layer represent the process technology.

See following example:

============

$$/*     layer  min_width       min_space*/

$$      ALMETAL 2       2

$$      TGM     0.4     0.4

$$      M5      0.063   0.063

$$      M4      0.063   0.063

$$      M3      0.063   0.063

$$      M2      0.063   0.063

$$      M1      0.063   0.063

$$      GC      0.04    0.09

 

 

$CONDUCTOR  GC              { THICKNESS=0.080000 WMIN=0.040000 SMIN=0.090000 RPSQ=17.000000 }

=============


This is a 40nm(cutting edge from 45nm).


What does '45-nm' mean

So today, "65 nm" or "45 nm" doesn't exactly refer to the line width, and certainly doesn't indicate how closely you can pack transistors together, although it does provide some indication of these things. Still, it is probably most accurate to say that the number is simply the name of the process, rather than the measure of any particular feature.


From http://www.edn.com/article/CA6493083.html

Sometimes a perfectly straightforward question has a perfectly messy answer. This is one of those times.

Originally, IC processes were named for the narrowest line that could be resolved by the printing equipment and the photoresist, and then successfully transformed into a feature on the surface of the wafer. In practical terms, this smallest feature was almost always the line that defined the gate electrode on the MOS transistor. So the name of a process became identified with the width of the gate electrode.

Just to make matters more complex, designers referred to this as the "gate length." (If you look at a transistor the way the current does, from one end through to the other, the width of the gate electrode determines the path length the current must traverse getting through the channel region.) Unfortunately for clarity, the gate length is also an approximate measure of transistor speed and of how densely you can pack transistors together in a hand-crafted layout.

Marketing departments seized upon the term as a measure of goodness, and quickly turned what had been a measure of a physical dimension into a measure of marketing bravado. The result was that by about 350 nm (actually called 0.35 micron in those days), the "350 nm" had become simply the name of the process rather than a measure of any physical dimension. The process might only be able to resolve a 380-nm line width, but through various other tricks, process engineers could get the transistors to behave as if their channel length were 350 nm. So it goes.

Today, the number has recovered some accuracy as a physical measure. A 65-nm process usually does have features—again, usually gate line widths—that are approximately 65 nm. There are exceptions. For instance, a company might design a process that will eventually be able to produce 65-nm lines, but for economic reasons they will leave out one or two critical pieces of equipment that would be necessary for the finest possible lines. They will usually announce this as a "65-nm" process, even though today it can't do 65-nm features.

The fascinating part today is that it is physically impossible for the printers, which work with 193-nm-wavelength light, to accurately transfer a 65-nm line from the mask to the wafer's surface. So designers use incredibly sophisticated tricks to make patterns on the mask that, when blurred and distorted by diffraction in the printing process, will end up being sort-of credible 65-nm-wide lines. These tricks include attaching "decorations" all over the line on the mask—bulges in the center, little whiskers at the corners, things that make a rectangle look more like an image in an ink-blot test. This in turn means that even if you can make one perfectly acceptable 65-nm-wide line, you may not be able to make another one right next to it. You may have to leave room for decorations in between.

So today, "65 nm" or "45 nm" doesn't exactly refer to the line width, and certainly doesn't indicate how closely you can pack transistors together, although it does provide some indication of these things. Still, it is probably most accurate to say that the number is simply the name of the process, rather than the measure of any particular feature.

Thursday, December 25, 2008

Cell Degradation Design Rule


The standard design rules (max_transition, max_fanout, and max_capacitance) cannot account for all reliability issues in deep submicron technologies.A new design rule was introduced to model this behavior more accurately.

The cell degradation design rule allows a maximum capacitance constraint to be based on the transition times at the cell inputs. The max_capacitance design rule takes precedence over cell degradation. Cell degradation can either be specified by the library vendor in their standard cell library or explicitly by the end user on the design's input ports.

By default, DC Ultra does not take into account cell degradation during optimization. To enable cell degradation analysis when using the set_cell_degradation command on design input ports, set the variable compile_fix_cell_degradation to true. If the cell degradation design rule is described in the library, you need to perform two steps. First, set compile_fix_cell_degradation to true, and second, use the set_ultra_optimization command described later in this document, to ensure you have a DC Ultra license. If you do not have a DC Ultra license during optimization, cell degradation design rules are ignored.

Timing Arc

Timing Arc Definition:

Timing arcs, along with netlist interconnect information, are the paths followed by the path tracer during path analysis.

Each timing arc has a startpoint and an endpoint.
  • The startpoint can be an input, output, or I/O pin.
  • The endpoint is always an output pin or an I/O pin.
  • The only exception is a constraint timing arc, such as a setup or hold constraint between two input pins.

There are two timing arc types:
  1. combinational timing arc: combinational timing arc information is used to calculate the physical delays in timing propagation and to trace paths. The timing analyzer uses path-tracing arcs for circuit timing analysis.
  2. sequential timing arc: sequential timing arc information is used to determine rule-based design optimization constraints.

Wednesday, December 24, 2008

cell degradation

A cell degradation design rule specifies the maximum capacitive load a cell can drive without causing cell performance degradation during the fall transition.

But I don't know the difference between cell degradation and max capacitance constraint rule:(


virtual clock

Virtual clock feature:
  • A clock that is not connected to any port or pin within the current design
  • Serves as a reference for input or output delays

difference between real clock and ideal clock

Above pic show the difference between ideal clock and real clock.

Difference between ideal clock and real clock contain following three part:
  1. latency
  2. uncertainty
  3. transition

Tuesday, December 23, 2008

Ideal Network Feature

Ideal Network Feature:
  • No DRC (capacitance, fanout, and transition) check for ideal net.
  • Zero pin capacitance and net capacitance for timing calculation.

For ideal clock feature, please refer to:
http://vlsi-concept.blogspot.com/2008/12/ideal-clock-feature.html

Clock Latency

Clock Latency contain following two parts:

Network Latency: net delay from clock port to flip-flop clock pin in the design.
Source Latency:   delay from clock source to design clock port.

See pic for detail information.

Ideal Clock has zero latency http://vlsi-concept.blogspot.com/2008/12/ideal-clock-feature.html




Definition of Timing Path

Definition of Timing Path:

Start point:

Input port
Clock pin of Flip-Flop or register

End point:

Output port
Any input pin of a sequential device, except clock pin1

See above pic for timing path examples.

Ideal Clock Feature

Feature of ideal clock:
  • Infinite drive capability
  • Zero rise/fall transition times
  • Zero skew
  • Zero insertion delay or latency
For ideal network feature: http://vlsi-concept.blogspot.com/2008/12/ideal-network-feature.html
For clock latency http://vlsi-concept.blogspot.com/2008/12/clock-latency.html

filter_collection 可以使用的操作符

概览

==, !=, >, <, >=, <=, =~, !~

解释

== 等于
!= 不等于
>  大于
<  小于
>= 大于等于
<= 小于等于
=~ 匹配
!~ 不匹配

difference between dc_shell and dc_shell-t

The "-t" extension invokes DC shell in Tcl-mode, which is the
recommended mode, and by default, also XG mode, which is also
recommended. Design Vision is ONLY available in TCL mode, hence no
"-t" extension is needed, and it also comes up in XG mode by default.

Monday, December 22, 2008

WLM- Wire load Model

在没有物理信息的时候,使用Wire load Model(WLM)模型可以算到net的电容,电阻等数据。
所以在DC中会使用WLM模型。

通常WLM模型会给出下面的一些参数:
单位长度电容
单位长度电阻
单位长度面积
外推斜率


模型例子:

wire_load("90x90") {
    capacitance : 2.0 ; /* C per unit-length */
    resistance :100.0 ; /* R per unit-length */
    area : 0.5 ; /* net-area per unit-length */
    slope : 1.5 ; /* extrapolation slope */
    fanout_length(1,1) ; /* fanout_length pairs */
    fanout_length(2,2.2);
    fanout_length(3,3.3);
    fanout_length(4,4.4);
}

根据fanout的数目可以得到net的长度,再算出相应的电容,电阻,面积等参数。


Design Compiler Topographical Technology

Topographical technology enables you to accurately predict post-layout timing, area, and power during RTL synthesis without the need for wireload model-based timing approximations. It uses Synopsys' placement and optimization technologies to drive accurate timing prediction within synthesis, ensuring better correlation to the final physical design. This new technology is built in as part of the DC Ultra feature set and is available only by using the compile_ultra command in topographical mode. Design Compiler topographical technology is shared with IC Compiler.

Synopsys Implementation Tool Guide

Synopsys Implementation Tool Guide
Design Compiler – Logic synthesis
Design Compiler Topographical -- DCT(new feature)
Physical Compiler
– Physical synthesis
JupiterXT – Floorplanning
Astro – Place and Route for designs down to 65nm design rules
IC Compiler – Next generation Place & Route
Power Compiler – Power optimizations for synthesis
PrimePower – Power analysis
PrimeRail – IR Drop and EM analysis
DFT Compiler – Scan synthesis
TetraMAX – Scan compression
PrimeTime – Signoff timing analysis
PrimeTime-SI – Signoff timing analysis with signal integrity effects
Astro-Rail – Signoff reliability analysis
Hercules – Physical verification
Star-RCXT – Parasitic extraction
HSPICE – Circuit simulation
NanoSim – Mixed signal circuit simulation